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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com cs5530 24-bit adc with ultra-low-noise amplifier features & description ? chopper-stabilized instrumentation amplifier, 64x ? 12 nv/ hz @ 0.1 hz (no 1/f noise) ? 500 pa input current ? digital gain scaling up to 40x ? delta-sigma analog-to-digital converter ? linearity error: 0.0015% fs ? noise free resolution: up to 19 bits ? scalable v ref input: up to analog supply ? simple three-wire serial interface ? spi? and microwire? compatible ? schmitt-trigger on serial clock (sclk) ? onboard offset and gain calibration registers ? selectable word rate s: 6.25 to 3,840 sps ? selectable 50 or 60 hz rejection ? power supply configurations ? va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v ? va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v ? va+ = +3 v; va- = -3 v; vd+ = +3 v general description the cs5530 is a highly integrated ? analog-to-digital converter (adc) which uses charge-balance techniques to achieve 24-bit performance. the adc is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. to accommodate these applications, the adc includes a very-low-noise, chopper- stabilized instrumentation amplifier (12 nv/ hz @ 0.1 hz) with a gain of 64x. this device also includes a fourth-order ? modulator fol- lowed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 sps (mclk = 4.9152 mhz). to ease communication between the adc and a micro- controller, the converter includes a simple three-wire se- rial interface which is spi and microwire compatible with a schmitt-trigger input on the serial clock (sclk). high dynamic range, programmable output rates, and flexible power supply options make this device an ideal solution for weigh scale and process control applications. ordering in formation see page 35. va+ c1 c2 vref+ vref- vd+ differential 4 th order ? modulator programmable sinc fir filter ain1+ ain1- serial interface latch clock generator calibration sram/control logic dgnd cs sdi sdo sclk osc2 osc1 a1 a0 va- 64x oct ?06 ds742a1
cs5530 2 ds742a1 table of contents 1. characteristics and specifications ................................................................. 4 analog characteristics................................................................................ 4 typical noise-free resolution (bit s), cs5530-cs................................... 6 5 v digital characteristics .......................................................................... 7 3 v digital characteristics .......................................................................... 7 dynamic characteristics .............................................................................. 8 absolute maximum ratings ........................................................................... 8 switching characteristics .......................................................................... 9 2. general description .............................................................................................. 11 2.1. analog input ........................................................................................................... 11 2.1.1. analog input span .......................................................................................... 12 2.1.2. voltage noise density performance ........................................................... 12 2.1.3. no offset dac ............................................................................................ 12 2.2. overview of adc register structure and operating modes .................................. 12 2.2.1. system initialization .................................................................................... 12 2.2.2. command register descriptions ................................................................ 14 2.2.3. serial port interface .................................................................................... 16 2.2.4. reading/writing on-chip registers ............................................................ 17 2.3. configuration register ........................................................................................... 17 2.3.1. power consumption ................................................................................... 17 2.3.2. system reset sequence ............................................................................ 17 2.3.3. input short .................................................................................................. 17 2.3.4. voltage reference select .......................................................................... 17 2.3.5. output latch pins ....................................................................................... 18 2.3.6. filter rate select ........................................................................................ 18 2.3.7. word rate select ........................................................................................ 18 2.3.8. unipolar/bipolar select ............................................................................... 18 2.3.9. open circuit detect .................................................................................... 18 2.3.10. configuration register description ........................................................... 19 2.4. calibration .............................................................................................................. 2 1 2.4.1. calibration registers .................................................................................. 21 2.4.2. gain register ............................................................................................. 21 2.4.3. offset register ........................................................................................... 21 2.4.4. performing calibrations .............................................................................. 22 2.4.5. system calibration ...................................................................................... 22 2.4.6. calibration tips ........................................................................................... 22 2.4.7. limitations in calibration range ................................................................. 23 2.5. performing conversions ........................................................................................ 23 2.5.1. single conversion mode ............................................................................. 23 2.5.2. continuous conversion mode .................................................................... 24 2.6. using multiple adcs synchronously ..................................................................... 25 2.7. conversion output coding .................................................................................... 25 2.7.1. conversion data output descriptions ........................................................ 26 2.8. digital filter ............................................................................................................ 27 2.9. clock generator ..................................................................................................... 28 2.10. power supply arrangements ................................................................................. 28 2.11. getting started ....................................................................................................... 31 2.12. pcb layout ............................................................................................................ 31 3. pin descriptions ...................................................................................................... 32 clock generator ......................................................................................................32 control pins and serial data i/o .............................................................................32 measurement and reference inputs ......................................................................33 power supply connections .....................................................................................33 4. specification definitions ..................................................................................... 33 5. package drawings .................................................................................................. 34 6. ordering information .......................................................................................... 35 7. environmental, manufacturing, & handling information .................... 35
cs5530 ds742a1 3 list of figures figure 1. sdi write timing (not to scale)............................................................................... 10 figure 2. sdo read timing (not to scale)... .......................................................................... 10 figure 3. front end configurat ion........................................................................................... 11 figure 4. input model for ain+ and ain- pins ......................................................................... 11 figure 5. measured voltage no ise density............................................................................. 12 figure 5. measured voltage no ise density............................................................................. 12 figure 6. cs5530 register diagram ................ ....................................................................... 13 figure 7. command and data word timing ........................................................................... 16 figure 8. input reference model when vrs = 1 .................................................................... 18 figure 9. input reference model when vrs = 0 .................................................................... 18 figure 10. system calibration of offset .................................................................................. 22 figure 11. system calibration of gain .................................................................................... 22 figure 12. synchronizing multiple adcs.......... ....................................................................... 25 figure 13. digital filter response (word rate = 60 sps) ....................................................... 27 figure 14. 120 sps filter magnitude plot to 120 hz ............................................................... 27 figure 15. 120 sps filter phase plot to 120 hz ...................................................................... 27 figure 16. z-transforms of digit al filters................................................................................ 27 figure 17. on-chip oscillator model........................................................................................ 28 figure 18. cs5530 configured wi th a single +5 v supply ..................................................... 29 figure 19. cs5530 configured with 2.5 v anal og supplies.................................................. 29 figure 20. cs5530 configured with 3 v analog supplies..................................................... 30 list of tables table 1. conversion timing for single mode ... ....................................................................... 24 table 2. conversion timing for continuous mo de.................................................................. 24 table 3. output coding ......................................................................................................... .. 25
cs5530 4 ds742a1 1. characteristics and specifications analog characteristics (va+, vd+ = 5 v 5%; vref+ = 5 v; va-, vref-, dgnd = 0 v; mclk = 4.9152 mhz; owr (output word rate) = 60 sps; bipolar mode) (see notes 1 and 2.) notes: 1. applies after system calibration at any temperature within 0 c to +70 c. 2. specifications guaranteed by design, charac terization, and/or test. lsb is 24 bits. 3. this specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. drift over specified temperature range after calibration at power-up at 25 c. parameter cs5530-cs unit min typ max accuracy linearity error - 0.0015 0.003 %fs no missing codes 24 - - bits bipolar offset - 16 32 lsb 24 unipolar offset - 32 64 lsb 24 offset drift (notes 3 and 4) - 10 - nv/c bipolar full-scale error - 8 31 ppm unipolar full-scale error - 16 62 ppm full-scale drift (note 4) - 2 - ppm/c
cs5530 ds742a1 5 analog characteristics (continued) (see notes 1 and 2.) notes: 5. see the section of the data sheet which discusses input models. 6. input current on vref+ or vref- may increase to 250 na if operated within 50 mv of va+ or va-. this is due to the rough charge buffer being saturated under these conditions. parameter min typ max unit analog input common mode + signal on ain+ or ain- bipolar/unipolar mode (va-) + 1.6 - (va+) - 1.6 v cvf current on ain+ or ain- - 1200 - pa input current noise - 0.4 - pa/ hz open circuit detect current 100 300 - na common mode rejection dc 50, 60 hz - - 130 120 - - db db input capacitance - 10 - pf voltage reference input range (vref+) - (vref-) 1 2.5 (va+)-(va-) v cvf current (note 5, 6) - 50 - na common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance 11 - 22 pf system calibration specifications full-scale calibration range bi polar/unipolar mode 3 - 110 %fs offset calibration range bipolar mode -100 - 100 %fs offset calibration range unipolar mode -90 - 90 %fs
cs5530 6 ds742a1 analog characteristics (continued) (see notes 1 and 2.) 7. all outputs unloaded. all input cmos levels. 8. tested with 100 mv change on va+ or va-. typical noise-free resolu tion (bits), cs5530-cs (see notes 9 and 10) 9. noise free resolution listed is for bipolar operation, and is calculat ed as log((input span)/(6.6xrms noise))/log(2) rounded to the nearest bit. for unipol ar operation, the input span is 1/2 as large, so one bit is lost. the input span is calculated in the ana log input span section of the data sheet. the noise free resolution table is co mputed with a value of 1.0 in the gain register. values other than 1.0 will scale the noise, and change the noise free resolution accordingly. 10. ?noise free resolution? is not the same as ?effec tive resolution?. effective resolution is based on the rms noise value, while noise free resolution is based on a peak-to- peak noise value specified as 6.6 times the rms noise value. effective resolu tion is calculated as log((input span)/(rms noise))/log(2). specifications are subject to change without notice. parameter cs5530-cs min typ max unit power supplies dc power supply currents (normal mode) i a+, i a- i d+ - - 7 0.5 9 1 ma ma power consumption normal mode (note 7) standby sleep - - - 40 5 500 50 - - mw mw w power supply rejection (note 8) dc positive supplies dc negative supply - - 115 115 - - db db output word rate (sps) -3 db filter frequency (hz) noise-free bits noise (nv rms ) 7.5 1.94 19 17 15 3.88 19 24 30 7.75 18 34 60 15.5 18 48 120 31 17 68 240 62 16 115 480 122 16 163 960 230 15 229 1,920 390 15 344 3,840 780 13 1390
cs5530 ds742a1 7 5 v digital characteristics (va+, vd+ = 5 v 5%; va-, dgnd = 0 v; see notes 2 and 11.) 3 v digital characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.0v1 0%; va-, dgnd = 0v; see notes 2 and 11.) 11. all measurements performed under static conditions. parameter symbol min typ max unit high-level input voltage all pins except sclk sclk v ih 0.6 vd+ (vd+) - 0.45 - - vd+ vd+ v low-level input voltage all pins except sclk sclk v il 0.0 0.0 -0.8 0.6 v high-level output voltage a0 and a1, i out = -1.0 ma sdo, i out = -5.0 ma v oh (va+) - 1.0 (vd+) - 1.0 -- v low-level output voltage a0 and a1, i out = 1.0 ma sdo, i out = 5.0 ma v ol - - (va-) + 0.4 0.4 v input leakage current i in -110a sdo 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit high-level input voltage all pins except sclk sclk v ih 0.6 vd+ (vd+) - 0.45 -vd+ vd+ v low-level input voltage all pins except sclk sclk v il 0.0 0.0 -0.8 0.6 v high-level output voltage a0 and a1, i out = -1.0 ma sdo, i out = -5.0 ma v oh (va+) - 1.0 (vd+) - 1.0 -- v low-level output voltage a0 and a1, i out = 1.0 ma sdo, i out = 5.0 ma v ol - - (va-) + 0.4 0.4 v input leakage current i in -110a sdo 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf
cs5530 8 ds742a1 dynamic characteristics 12. the adcs use a sinc 5 filter for the 3200 sps and 3840 sps output word rate (owr) and a sinc 5 filter followed by a sinc 3 filter for the other owrs. owr sinc5 refers to the 3200 sps (frs = 1) or 3840 sps (frs = 0) word rate associated with the sinc 5 filter. 13. the single conversion mode only outputs fully se ttled conversions. see table 1 for more details about single conversion mode timing. owr sc is used here to designate the different conversion time associated with single conversions. 14. the continuous conversion mode ou tputs every conversion. this means that the filter?s settling time with a full-scale step input in the continuous conversion mode is dictated by the owr. absolute maximum ratings (dgnd = 0 v; see note 15.) notes: 15. all voltages with respect to ground. 16. va+ and va- must satisfy {(va+) - (va-)} +6.6 v. 17. vd+ and va- must sati sfy {(vd+) - (va-)} +7.5 v. 18. applies to all pins including continuous overvo ltage conditions at the analog input (ain) pins. 19. transient current of up to 100 ma will not cause scr latch-up. ma ximum input current for a power supply pin is 50 ma. 20. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol ratio unit modulator sampling rate f s mclk/16 sps filter settling time to 1/ 2 lsb (full-scale step input) single conversion mode (notes 12, 13, and 14) continuous conversion mode, owr < 3200 sps continuous conversion mode, owr 3200 sps t s t s t s 1/owr sc 5/owr sinc5 + 3/owr 5/owr s s s parameter symbol min typ max unit dc power supplies (notes 16 and 17) positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 +0.3 - - - +6.0 +6.0 -3.75 v v v input current, any pin except supplies (notes 18 and 19) i in --10ma output current i out --25ma power dissipation (note 20) pdn - - 500 mw analog input voltage vref pins ain pins v inr v ina (va-) -0.3 (va-) -0.3 - - (va+) + 0.3 (va+) + 0.3 v v digital input voltage v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a 0-70c storage temperature t stg -65 - 150 c
cs5530 ds742a1 9 switching characteristics (va+ = 2.5 v or 5 v 5%; va- = -2.5v 5% or 0 v; vd+ = 3.0 v 10% or 5 v 5%;dgnd = 0 v; levels: logic 0 = 0 v, logic 1 = vd+; c l = 50 pf; see figures 1 and 2.) notes: 21. device parameters are specified with a 4.9152 mhz clock. 22. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 23. oscillator start-up time varies with crystal parameters. this specificat ion does not apply when using an external clock source. parameter symbol min typ max unit master clock frequency (note 21) external clock or crystal oscillator mclk 1 4.9152 5 mhz master clock duty cycle 40 - 60 % rise times (note 22) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 22) any digital input except sclk sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 4.9152 mhz (note 23) t ost -20-ms serial port timing serial clock frequency sclk 0 - 2 mhz serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to valid latch clock t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 --150ns sclk falling to new data bit t 8 --150ns cs rising to sdo hi-z t 9 --150ns
cs5530 10 ds742a1 cs sclk msb msb-1 lsb sdi t3 t6 t4 t5 t1 t2 figure 1. sdi write timing (not to scale) cs sclk msb msb-1 lsb sdo t7 t9 t8 t1 t2 figure 2. sdo read timing (not to scale)
cs5530 ds742a1 11 2. general description the cs5530 is a ? analog-to-digital converter (adc) which uses charge-balance techniques to achieve 24-bit performan ce. the adc is optimized for measuring low-level uni polar or bipolar signals in weigh scale, process c ontrol, scientific, and med- ical applications. to accommodate these applications, the adc in- cludes a very-low- noise, chopper-stabilized instru- mentation amplifier (12 nv/ hz @ 0.1 hz) with a gain of 64x. this adc al so includes a fourth-order ? modulator followed by a digital filter which pro- vides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 samples per second (mclk = 4.9152 mhz). to ease communication be tween the adcs and a micro-controller, the c onverters include a simple three-wire serial interfa ce which is spi and mi- crowire compatible with a schmitt-trigger input on the serial clock (sclk). 2.1 analog input figure 3 illustrates a block diagram of the cs5530. the front end includes a chopper-stabilized instru- mentation amplifier with a gain of 64x. the amplifier is chopper- stabilized and operates with a chop clock frequency of mclk/128. the cvf (sampling) current into the instrumentation amplifier is typically 1200 pa over 0c to +70c (mclk=4.9152 mhz). the common-mode plus signal range of the inst rumentation amplifier is (va-) + 1.6 v to (va+) - 1.6 v. figure 4 illustrates the input model for the 64x am- plifier. note: the c = 14pf capacitor is for input current modeling only. for physical input capacitance see ?input capacitance? specification under analog characteristics . vref+ sinc digital filter 64x ain+ ain- x1 vref- x1 differential 4 order ? modulator th 5 programmable sinc digital filter 3 serial port 1000 ? 1000 ? 22 nf c1 pin c2 pin figure 3. front end configuration ain c = 14 pf coarse 1 fine 1 v 12 mv i = fv c os os n f = mclk 16 figure 4. input model for ain+ and ain- pins
cs5530 12 ds742a1 2.1.1 analog input span the full-scale input signal th at the converter can dig- itize is a function of the reference voltage connected between the vref+ and vr ef- pins. the full-scale input span of the converter is ((vref+) ? (vref-))/(64y), where 64 is the gain of the amplifier and y is 2 for vrs = 0, or y is 1 for vrs = 1. vrs is the voltag e reference select bit, and must be set according to the differential voltage applied to the vref+ and vref- pins on the part. see section 2.3.4 for more details. with a 2.5 v reference, th e full-scale biploar input range is equal to 2.5/64, or about 39 mv. note that these input ranges as sume the calibration regis- ters are set to their defaul t values (i.e. gain = 1.0 and offset = 0.0). the gain setting in the gain register can be altered to map the digital codes of the con- verter to set full sc ales from 1 mv to 40 mv. 2.1.2 voltage noise density performance figure 5 illustrates the m easured voltage noise den- sity versus frequency from 0.1 hz to 10 hz. the de- vice was powered with 2.5 v supplies, using 120 sps owr, bipolar m ode, and with the input short bit enabled. 2.1.3 no offset dac an offset dac was not in cluded in the cs5530 be- cause the high dynamic range of the converter eliminates the need for one . the offset register can be manipulated by the user to mimic the function of a dac if desired. 2.2 overview of adc register structure and operating modes the cs5530 adc has an on-chip controller, which includes a number of user-a ccessible registers. the registers are used to hold offset and gain calibration results, configure the chip 's operating modes, hold conversion instructions, and to store conversion data words. figure 6 depi cts a block diagram of the on-chip controller?s internal registers. the converter has 32-bit regi sters to function as the offset and the gain calibra tion registers. these reg- isters hold calibration result s. the contents of these registers can be read or wr itten by the user. this al- lows calibration data to be off-loaded into an exter- nal eeprom. the user can also manipulate the contents of these register s to modify the offset or the gain slope of the converter. the converter includes a 32-bit configuration reg- ister which is used for se tting options such as the power down modes, resetting the converter, short- ing the analog input, enabling logic outputs, and other user options. the following pages document how to initialize the converter and perform offs et and gain calibrations. each of the bits of the conf iguration register is de- scribed. also the command register quick refer- ence can be used to decode all valid commands (the first 8-bits into the serial port). 2.2.1 system initialization the cs5530 provide no pow er-on-reset function. to initialize the adc, the us er must perform a soft- ware reset via the confi guration register. before accessing the configuration register, the user must insure serial port synchr onization by using the se- rial port initialization se quence. this sequence re- sets the serial port to the command mode and is accomplished by transmit ting at least 15 sync1 command bytes (0xff hexadecimal), followed by one sync0 command (0xf e hexadecimal). note that this sequence can be initiated at anytime to reinitialize the serial port . to complete the system 1.0 10.0 100.0 0.1 1 10 frequency (hz) nv/ hz figure 5. measured voltage noise density
cs5530 ds742a1 13 initialization sequence, the user must also perform a system reset sequence whic h is as follows: write a logic 1 into the rs bit of the configuration regis- ter. this will reset the calibration registers and other logic (but not the se rial port). a valid reset will set the rv bit in the configuration register to a logic 1. after writing the rs bit to a logic 1, wait 8 master clock cycles, then write the rs bit back to logic 0. note that the ot her bits in the configura- tion register cannot be wr itten on this write cycle as they are being held in reset until rs is set back to logic 0. while this i nvolves writing an entire word into the configurati on register to casue the rs bit to go to logic 0, the rv bit is a read only bit, therefore a write to the c onfiguration register will not overwrite the rv bit. after clearing the rs bit back to logic 0, read the configuration register to check the state of the rv bi t as this indicates that a valid reset occurred. re ading the configuration register clears the rv bit back to logic 0. completing the reset cycle initializes the on-chip registers to the following states: after the configuration re gister has been read to clear the rv bit, the regist er can then be written to set the other function bits or other registers can be written or read. once the system initialization or reset is complet- ed, the on-chip controller is initialized into com- mand mode where it waits for a valid command (the first 8-bits written into the serial port are shift- ed into the command register). once a valid com- mand is received and decoded, the byte instructs the converter to either acqui re data from or transfer data to an internal regist er, or perform a conversion or a calibration. the command register descrip- tions section lists all valid commands. offset (1 x 32) offset register (1 x 32) conversion data register (1 x 32) configuration register (1 x 32) power save select reset system input short voltage reference select output latch cs sdi sdo sclk read only command register (1 8) write only serial interface data (1 x 32) filter rate select word rate unipolar/bipolar open circuit detect gain (1 x 32) gain register (1 x 32) figure 6. cs5530 register diagram configuration register: 00000000(h) offset register: 00000000(h) gain register 01000000(h)
cs5530 14 ds742a1 2.2.2 command register descriptions read/write offset register r/w (read/write) 0 write offset register. 1 read offset register. read/write gain register r/w (read/write) 0 write gain register. 1 read gain register. read/write configuration register function: these commands are used to read from or write to the configuration register. r/w (read/write) 0 write configuration register. 1 read configuration register. perform conversion mc (multiple conversions) 0 perform a single conversion. 1 perform continuous conversions. perform system of fset calibration perform system ga in cali bration sync1 function: part of the serial port re-initialization sequence. d7(msb) d6 d5 d4 d3 d2 d1 d0 0000r/w 001 d7(msb) d6 d5 d4 d3 d2 d1 d0 0000r/w 010 d7(msb) d6 d5 d4 d3 d2 d1 d0 0000r/w 011 d7(msb) d6 d5 d4 d3 d2 d1 d0 1mc000000 d7(msb) d6 d5 d4 d3 d2 d1 d0 10000101 d7(msb) d6 d5 d4 d3 d2 d1 d0 10000110 d7(msb) d6 d5 d4 d3 d2 d1 d0 11111111
cs5530 ds742a1 15 sync0 function: end of the serial port re-initialization sequence. null function: this command is used to clear a port flag and keep the converter in the continuous conversion mode. d7(msb) d6 d5 d4 d3 d2 d1 d0 11111110 d7(msb) d6 d5 d4 d3 d2 d1 d0 00000000
cs5530 16 ds742a1 2.2.3 serial port interface the cs5530?s serial interface consists of four con- trol lines: cs , sdi, sdo, sclk . figure 7 details the command and data word timing. cs , chip select, is the control line which enables access to the serial port. if the cs pin is tied low, the port can function as a three wire interface. sdi, serial data in, is th e data signal used to trans- fer data to the converters. sdo, serial data out, is the data signal used to transfer output data from the converters. the sdo output will be held at high impedance any time cs is at logic 1. sclk, serial clock, is th e serial bit-clock which controls the shifting of da ta to or from the adc?s serial port. the cs pin must be held low (logic 0) before sclk transitions can be recognized by the port logic. to accommodat e optoisolators sclk is designed with a schmitt-tr igger input to allow an optoisolator with slower ri se and fall times to di- rectly drive the pin. addi tionally, sdo is capable of sinking or sourcing up to 5 ma to directly drive an optoisolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourc- ing 5 ma. command time 8sclks data time 32 sclks write cycle cs sclk sdi msb command time 8sclks cs sclk sdi read cycle sdo msb lsb command time 8sclks 8 sclks clear sdo flag sdo sclk sdi msb lsb clock cycles t* d cs data time 32 sclks data time 32 sclks lsb data conversion cycle /owr mclk * td is the time it takes the adc to perform a conversion. see the single conversion and continuous conversion sections of the data sheet for more details about conversion timing. figure 7. command and data word timing
cs5530 ds742a1 17 2.2.4 reading/writing on-chip registers the cs5530?s offset, gain, and configuration regis- ters are readable and writable while the conversion data register is read only. as shown in figure 7, to wr ite to a particular regis- ter the user must transmit the appropriate write command and then follow that command by 32 bits of data. for example, to write 0x80000000 (hexa- decimal) to the gain regi ster, the user would first transmit the command byte 0x02 (hexadecimal) followed by the data 0x80000000 (hexadecimal). similarly, to read a particul ar register the user must transmit the appropriate read command and then acquire the 32 bits of data. once a register is written to or read from, the serial port returns to the com- mand mode. 2.3 configuration register to ease the architectural design and simplify the serial interface, the configur ation register is thirty- two bits long, however, only fifteen of the thirty two bits are used. the foll owing sections detail the bits in the configuration register. 2.3.1 power consumption the cs5530 accommodates three power consump- tion modes: normal, sta ndby, and sleep. the default mode, ?normal mode?, is en tered after power is ap- plied. in this mode, the cs5530 typically consumes 35 mw. the other two modes are referred to as the power save modes. they power down most of the analog portion of the chip and stop filter convolu- tions. the power save m odes are entered whenever the power down (pdw) bit of the configuration register is set to logic 1. the particular power save mode entered depends on state of the pss (power save select) bit. if pss is logic 0, the converter en- ters the standby mode reducing the power con- sumption to 4 mw. the st andby mode leaves the oscillator and the on-chip bias generator for the an- alog portion of the chip activ e. this allows the con- verter to quickly return to the normal mode once pdw is set back to a l ogic 0. if pss and pdw are both set to logic 1, the slee p mode is entered reduc- ing the consumed power to around 500 w. since this sleep mode disables the oscillator, approxi- mately a 20 ms oscillator start-up delay period is required before returning to the normal mode. if an external clock is used, there will be no delay. 2.3.2 system reset sequence the reset system (rs) bit permits the user to per- form a system reset. a system reset can be initiated at any time by writ ing a logic 1 to the rs bit in the configuration register. af ter the rs bit has been set, the internal logic of the chip will be initialized to a reset state. the reset valid (rv) bit is set indi- cating that the internal logic was properly reset. the rv bit is cleared afte r the configuration regis- ter is read. the on-chip registers are initialized to the following default states: after reset, the rs bit should be written back to logic 0 to complete the reset cycle. the adc will return to the command mode where it waits for a valid command. also, the rs bit is the only bit in the configuration register that can be set when ini- tiating a reset (i.e. a sec ond write command is need- ed to set other bits in the configuration register after the rs bit has been cleared). 2.3.3 input short the input short bit allows the user to internally ground the inputs of the adc. this is a useful func- tion because it allows the user to easily test the grounded input performanc e of the adc and elim- inate the noise effects due to the external system components. 2.3.4 voltage reference select the voltage reference sele ct (vrs) bit selects the size of the sampling capacitor used to sample the voltage reference. the bi t should be set based upon configuration register: 00000000(h) offset register: 00000000(h) gain register 01000000(h)
cs5530 18 ds742a1 the magnitude of the reference voltage to achieve optimal performance. figur es 8 and 9 model the ef- fects on the reference?s input impedance and input current for each vrs sett ing. as the models show, the reference includes a co arse/fine charge buffer which reduces the dynamic current demand of the external reference. the reference?s input buffer is designed to accom- modate rail-to-rail (comm on-mode plus signal) in- put voltages. the differential voltage between the vref+ and vref- can be any voltage from 1.0 v up to the analog supply (depending on how vrs is configured), however, the vref+ cannot go above va+ and the vref- pin can not go below va-. note that the power supplies to the chip should be established before the reference voltage. 2.3.5 output latch pins the a1-a0 pins of the adc mimic the d24-d23 bits of the configurati on register. a1-a0 can be used to control external multiplexers and other log- ic functions outside the converter. the a1-a0 out- puts can sink or source at least 1 ma, but it is recommended to limit driv e currents to less than 20 a to reduce self-heating of the chip. these out- puts are powered from va + and va-. their output voltage will be limited to the va+ voltage for a logic 1 and va- for a logic 0. note that if the latch bits are used to modify the analog input signal the user should delay perfor ming a conversion until he knows the effects of the a0/a1 bits are fully set- tled. 2.3.6 filter rate select the filter rate select bit (frs) modifies the output word rates of the converter to allow either 50 hz or 60 hz rejection when operating from a 4.9152 mhz crystal. if frs is cl eared to logic 0, the word rates and corresponding filt er characteri stics can be selected using the confi guration register. rates can be 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, or 3840 sps when using a 4.9152 mhz clock. if frs is set to logic 1, the wo rd rates and corresponding filter characteristics scal e by a factor of 5/6, mak- ing the selectable wo rd rates 6.25, 12.5, 25, 50, 100, 200, 400, 800, 1600, and 3200 sps when using a 4.9152 mhz clock. when us ing other clock fre- quencies, these selectable word rates will scale lin- early with the clock frequency that is used. 2.3.7 word rate select the word rate select bi ts (wr3-wr0) allow slec- tion of the output word rate of the converter as de- picted in the configurati on register descriptions. the word rate chosen by the wr3-wr0 bits is modified by the setting of the frs bit as presented in the previous paragraph. 2.3.8 unipolar/bipolar select the up/bp select bit sets the converter to measure either a unipolar or bipolar input span. 2.3.9 open circuit detect when the ocd bit is set it activates a current source as a means to test for open thermocouples. vref c=14pf f= 2 fine 1 v 8mv i=fv c os os n coarse mclk 16 vrs = 1; 1 v v 2.5 v ref figure 8. input reference model when vrs = 1 vref c= 7pf f= 2 fine 1 v 16 mv i=fv c os os n coarse mclk 16 vrs = 0; 2.5 v < v va+ ref figure 9. input reference model when vrs = 0
cs5530 ds742a1 19 2.3.10 configuration register description pss (power save select)[31] 0 standby mode (oscillator active, allows quick power-up). 1 sleep mode (oscillator inactive). pdw (power down mode)[30] 0 normal mode 1 activate the power save select mode. rs (reset system)[29] 0 normal operation. 1 activate a reset cycle. see system re set sequence in t he datasheet text. rv (reset valid)[28] 0 normal operation 1 system was reset. this bit is read only. bit is cleared to logic zero after the configuration register is read. is (input short)[27] 0 normal input 1 all signal input pairs for each channel are disco nnected from the pins and shorted internally. nu (not used)[26] 0 must always be logic 0. reserved for future upgrades. vrs (voltage reference select)[25] 0 2.5 v < v ref [(va+) - (va-)] 11 v v ref 2.5v a1-a0 (output latch bits)[24:23] the latch bits (a1 and a0) will be set to the logic state of these bits when the configuration register is written. note that these logic outputs are powered from va+ and va-. 00 a1 = 0, a0 = 0 01 a1 = 0, a0 = 1 10 a1 = 1, a0 = 0 11 a1 = 1, a0 = 1 nu (not used)[22:20] 0 must always be logic 0. reserved for future upgrades. filter rate select, frs[19] 0 use the default output word rates. 1 scale all output word rates and their correspondi ng filter characteristics by a factor of 5/6. nu (not used)[18:15] 0 must always be logic 0. reserved for future upgrades. d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 pss pdw rs rv is nu vrs a1 a0 nu nu nu frs nu nu nu d15 d14d13d12d11d10d9 d8d7d6d5d4d3d2d1d0 nu wr3 wr2 wr1 wr0 up/bp ocdnununununununununu
cs5530 20 ds742a1 wr3-wr0 (word rate) [14:11] the listed word rates are for continuous conversion mode using a 4.9152 mhz clock. all word rates will scale linearly with the clock frequency used. the very first conversion using continuous conversion mode will last longer, as will conversions done with the si ngle conversion mode. see the section on performing conversions and tables 1 and 2 for more details. bit wr (frs = 0) wr (frs = 1) 0000 120 sps 100 sps 0001 60 sps 50 sps 0010 30 sps 25 sps 0011 15 sps 12.5 sps 0100 7.5 sps 6.25 sps 1000 3840 sps 3200 sps 1001 1920 sps 1600 sps 1010 960 sps 800 sps 1011 480 sps 400 sps 1100 240 sps 200 sps all other combinations are not used. u/b (unipolar / bipolar) [10] 0 select bipolar mode. 1 select unipolar mode. ocd (open circuit detect bit) [9] when set, this bit activates a 300 na current source on the input channel (ain+) selected by the channel select bits. note that the 300na current source is rated at 25c. this feat ure is particularly useful in ther- mocouple applications when the user wants to driv e a suspected open thermocouple lead to a supply rail. 0 normal mode. 1 activate current source. nu (not used) [8:0] 0 must always be logic 0. reserved for future upgrades.
cs5530 ds742a1 21 2.4 calibration calibration is used to set the zero and gain slope of the adc?s transfer function. the cs5530 provides system calibration. note: after the adc is reset, it is functional and can perform measurements without being calibrated (remember that the vrs bit in the configuration register must be properly configured). if the converter is operated without calibraton, the converter will utilize the initialized values of the on-chip registers (offset = 0.0; gain = 1.0) to calculate output words. any initial offset and gain errors in the internal circuitry of the chip will remain. 2.4.1 calibration registers the cs5530 converter has an offset register that is used to set the zero point of the converter?s transfer function. as shown in offset register section, one lsb in the offset register is 1.835007966 x 2 -24 proportion of the input span (bipolar span is 2 times the unipolar span, gain register = 1.000...000 deci- mal). the msb in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). no te that the magnitude of the offset that is trimmed from the input is mapped through the gain register. the converter can typi- cally trim 100 percent of the input span. as shown in the gain register section, the gain register spans from 0 to (64 - 2 -24 ). the decimal equivalent mean- ing of the gain register is where the binary numbers have a value of either zero or one (b d29 is the binary value of bit d29). while gain register se ttings of up to 64 - 2 -24 are available, the gain regist er should never be set to values above 40. 2.4.2 gain register the gain register span is from 0 to (64-2 -24 ). after reset d24 is 1, all other bits are ?0?. 2.4.3 offset register one lsb represents 1.835007966 x 2 -24 proportion of the input span (bi polar span is 2 times unipolar span). offset and data word bits align by msb. after reset, all bits are ?0?. the offset register is stored as a 32-bit, two?s complement number, where the last 8 bits are all 0. db d 29 2 5 b d 28 2 4 b d 27 2 3 b d 0 2 24 ? ) ++++ b di 2 24 ? i + () i 0 = 29 == decimal point msb d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 nu nu 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 0000000100000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 22 2 -23 2 -24 0000000000000000 msb d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 sign 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 0000000000000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 nu nu nu nu nu nu nu nu 0000000000000000
cs5530 22 ds742a1 2.4.4 performing calibrations to perform a calibration, th e user must send a com- mand byte with its msb=1, and the appropriate calibration bits (cc2-cc0 ) set to choose the type of calibration to be perf ormed. the calibration will be performed using the filt er rate, and siganl span (unipolar or bipolar) as se t in the configuration reg- ister. the length of time it takes to do a calibration is slightly less than the am ount of time it takes to do a single conversion (see ta ble 1 for single conver- sion timing). offs et calibration takes 608 clock cy- cles less than a single conversion when frs = 0, and 729 clock cycles less when frs = 1. gain cal- ibration takes 128 clock cy cles less than a single conversion when frs = 0, and 153 clock cycles less when frs = 1. once a calibration cycle is complete, sdo falls and the results are automatically stored in either the gain or offset register. sdo will remain low until the next command word is begun. if additional cal- ibrations are performed wh ile referencing the same calibration registers, the last calibration results will replace the effects from the previous calibration. only one calibration is performed with each com- mand byte. 2.4.5 system calibration for the system calibrati on functions, the user must supply the converter input calibration signals which represent ground and full-scal e. when a system off- set calibration is performe d, a ground referenced sig- nal must be applied to the converter. figure 10 illustrates system offset calibration. as shown in figure 11, the user must input a signal representing the positive full -scale point to perform a system gain calibration. in either case, the cali- bration signals must be wi thin the specified calibra- tion limits for each specific calibration step (refer to the system calibration specifications ). 2.4.6 calibration tips calibration steps are perf ormed at the output word rate selected by the wr3- wr0 bits of the configu- ration register. to minimi ze the effects of peak-to- peak noise on the accuracy of calibration the con- verter should be calibrated using the slowest word rate that is acc eptable. it is recommended that word rates of 240 sps a nd higher not be used for calibration.) to minimize di gital noise near the de- vice, the user should wait for each calibration step to be completed before read ing or writing to the se- rial port. reading the cali bration registers and aver- aging multiple calibrations together can produce a more accurate calibration result. note that access- ing the adc?s serial port before a calibration has finished may result in the loss of synchronization between the microcontroll er and the adc, and may prematurely halt the calibration cycle. figure 10. system calibration of offset figure 11. system calibration of gain
cs5530 ds742a1 23 for maximum accuracy, calib rations should be per- formed for both offset and gain. when the device is used without calibration, the uncalibrated gain accuracy is about 1 percent. note that the gain from the offset register to the output is 1.83007966 decimal, not 1. if a user wants to adjust the calibration coefficients externally, they will need to divide the information to be writ- ten to the offset regist er by the scale factor of 1.83007966. (this discussion as sumes that the gain register is 1.000...000 decima l. the offset register is also multiplied by the ga in register before being applied to the output conversion words). 2.4.7 limitations in calibration range system calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the analog input section of this data sheet. for gain calibration, the full-scale input signal can be reduced to 3% of the nominal full- scale value. at this point, the gain register is ap- proximately equal to 33.33 (decimal). while the gain register can hold numbers all the way up to 64 - 2 -24 , gain register sett ings above a decimal value of 40 should not be used. with the convert- er?s intrinsic gain error, this minimum full-scale in- put signal may be higher or lower. in defining the minimum full-scale cali bration range (fscr) un- der analog characteristics , margin is retained to accommodate the intrinsic ga in error. inversely, the input full-scale signal can be increased to a point in which the modulator reache s its 1?s density limit of 86 percent, which under nom inal conditions occurs when the full-scale input signal is 1.1 times the nominal full-scale value. wi th the chip?s intrinsic gain error, this maximum full-scale input signal maybe higher or lower. in defining the maximum fscr, margin is again incorporated to accommo- date the intrinsic gain error. 2.5 performing conversions the cs5530 offers two dist inctly different conver- sion modes. the paragraphs that follow detail the differences in th e conversion modes. 2.5.1 single conversion mode when the user transmits the perform single conver- sion command, a single, fu lly settled conversion is performed using the word rate and polarity selec- tions set in the configur ation register. once the command byte is transmitte d, the serial port enters data mode where it wait s until the conversion is complete. when the convers ion data is available, sdo falls to logic 0 to act as a flag to indicate that the data is available. fo rty sclks are then needed to read the conversion data word. the first 8 sclks are used to clear the sdo flag. during the first 8 sclks, sdi must be logic 0. the last 32 sclks are needed to read the conversion result. note that the user is forc ed to read the conversion in single conversi on mode as the seri al port will re- main in data mode until sclk transitions 40 times. after reading the data, the serial port returns to the command mode, where it waits for a new command to be issued. the single conversion mode will take longer than conversions performed in the continu- ous conversion mode. the number of clock cycles a single conversion takes for each output word rate (owr) setting is listed in table 1. the 8 (frs = 0) or 10 (frs = 1) clock ambiguity is due to internal synchronizati on between the sclk in- put and the oscillator. note: in the single conversion mode, more than one conversion is actually performed, but only the final, fully settled result is output to the conversion data register.
cs5530 24 ds742a1 2.5.2 continuous conversion mode when the user transmit s the perform continuous conversion command, the c onverter begins contin- uous conversions using the word rate and polarity selections set in the co nfiguration register. once the command byte is transmitted, the serial port en- ters data mode where it waits until a conversion is complete. after the conversion is done, sdo falls to logic 0 to act as a flag to indicate that the data is available. forty sclks are then needed to read the conversion. the first 8 sclk s are used to clear the sdo flag. the last 32 sc lks are needed to read the conversion result. if ?00000000? is provided to sdi during the firs t 8 sclks when the sdo flag is cleared, the converter rema ins in this conversion mode and continues to c onvert using the same word rate and polarity inform ation. in continuous con- version mode, not every conversion word needs to be read. the user needs onl y to read the conversion words required for the appl ication as sdo rises and falls to indicate the ava ilability of new conversion data. note that if a convers ion is not read before the next conversion data become s available, it will be lost and replaced by th e new conversion data. to exit this conversion mode , the user must provide ?11111111? to the sdi pin during the first 8 sclks after sdo falls. if the user decides to exit, 32 sclks are required to cloc k out the last conversion before the converter returns to command mode. the number of clock cycl es a continuous conver- sion takes for each output word setting is listed in table 2. the first conversion from the part in con- tinuous conversion mode wi ll be longer than the following conversi ons due to start-up overhead. the 8 (frs = 0) or 10 (frs = 1) clock ambigu- ity is due to internal s ynchronization between the sclk input and the oscillator. note: when changing channels, or after performing calibrations and/or single conversions, the user must ignore the first three (for owrs less than 3200 sps, mclk = 4.9152 mhz) or first five (for owr 3200 sps) conversions in continuous conversion mode, as residual filter coefficients must be flushed from the filter before accurate conversions are performed. table 1. conversion timing for single mode (wr3-wr0) clock cycles frs = 0 frs = 1 0000 171448 8 205738 10 0001 335288 8 402346 10 0010 662968 8 795562 10 0011 1318328 8 1581994 10 0100 2629048 8 3154858 10 1000 7592 8 9110 10 1001 17848 8 21418 10 1010 28088 8 33706 10 1011 48568 8 58282 10 1100 89528 8 107434 10 table 2. conversion timing for continuous mode frs (wr3-wr0) clock cycles (first conversion) clock cycles (all other conversions) 0 0000 89528 8 40960 0 0001 171448 8 81920 0 0010 335288 8 163840 0 0011 662968 8 327680 0 0100 1318328 8 655360 0 1000 2472 8 1280 0 1001 12728 8 2560 0 1010 17848 8 5120 0 1011 28088 8 10240 0 1100 48568 8 20480 1 0000 107434 10 49152 1 0001 205738 10 98304 1 0010 402346 10 196608 1 0011 795562 10 393216 1 0100 1581994 10 786432 1 1000 2966 10 1536 1 1001 15274 10 3072 1 1010 21418 10 6144 1 1011 33706 10 12288 1 1100 58282 10 24576
cs5530 ds742a1 25 2.6 using multiple adcs synchronously some applications requi re synchronous data out- puts from multiple adcs converting different ana- log channels. multiple cs5530 devices can be synchronized in a single system by using the fol- lowing guidelines: 1) all of the adcs in the system must be operated from the same oscillator source. 2) all of the adcs in the system must share com- mon sclk and sdi lines. 3) a software reset must be performed at the same time for all of the adcs after system power-up (by selecting all of the adcs using their respective cs pins, and writing the reset sequence to all parts, us- ing sdi and sclk). 4) a start conversion comma nd must be sent to all of the adcs in the system at the same time. the 8 clock cycles of ambiguity for the first conversion (or for a single conversion) will be the same for all adcs, provided that they we re all reset at the same time. 5) conversions can be obtained by monitoring sdo on only one adc, (bring cs high for all but one part) and reading the data out of each part indi- vidually, before the next conversion data words are ready. an example of a synchronous system using two cs5530 devices is shown in figure 12. 2.7 conversion output coding the cs5530 outputs 24-bit da ta conversion words. to read a conversion word the user must read the conversion data register. the conversion data reg- ister is 32 bits long a nd outputs the conversions msb first. the last byte of the conversion data reg- ister contains an overflo w flag bit. the overrange flag (of) monitors to de termine if a valid conver- sion was performed. the cs5530 output data conversions in binary for- mat when operating in unipol ar mode and in two's complement when operati ng in bipolar mode. ta- ble 3 shows the code mappi ng for both unipolar and bipolar modes. vfs in the tables refers to the posi- tive full-scale voltage range of the converter in the specified gain range, and -vfs refers to the nega- tive full-scale voltage ra nge of the converter. the total differential input range (between ain+ and ain-) is from 0 to vfs in unipolar mode, and from -vfs to vfs in bipolar mode. clock source cs5530 cs5530 sdo sdi sclk cs osc2 sdo sdi sclk cs osc2 c figure 12. synchronizing multiple adcs table 3. output coding unipolar input voltage offset binary bipolar input voltage two's complement >(vfs-1.5 lsb) ffffff >(vfs-1.5 lsb) 7fffff vfs-1.5 lsb ffffff ------ fffffe vfs-1.5 lsb 7fffff ------ 7ffffe vfs/2-0.5 lsb 800000 ------ 7fffff -0.5 lsb 000000 ------ ffffff +0.5 lsb 000001 ------ 000000 -vfs+0.5 lsb 800001 ------ 800000 <(+0.5 lsb) 000000 <(-vfs+0.5 lsb) 800000
cs5530 26 ds742a1 2.7.1 conversion data output descriptions cs5530 (24-bit conversions) conversion data bits [31:8] these bits depict the latest output conversion. of (over-range flag bit) [2] 0 bit is clear when over-range condition has not occurred. 1 bit is set when input signal is more positive than th e positive full-scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full-scale (bipolar mode). other bits [7:3], [1:0] these bits are masked logic zero. d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 msb 2221201918 17 16151413121110 9 8 d15 d14d13d12d11d10d9 d8d7d6d5d4d3d2d1d0 7 65432 1lsb00000of00
cs5530 ds742a1 27 2.8 digital filter the cs5530 has a linear phase digital filter which is programmed to achieve a range of output word rates (owrs) as stated in the configuration regis- ter description section. the adc uses a sinc 5 dig- ital filter to output wo rd rates at 3200 sps and 3840 sps (mclk = 4.9152 mhz). other output word rates are achieved by using the sinc 5 filter followed by a sinc 3 filter with a pr ogrammable decimation rate.figure 13 shows the ma gnitude response of the 60 sps filter, while figu res 14 and 15 show the magnitude and phase respons e of the filter at 120 sps. the sinc 3 is active for all output word rates except for the 3200 sp s and 3840 sps (mclk = 4.9152 mhz) rate. the z-tran sforms of the two fil- ters are shown in figure 16. for the sinc 3 filter, ?d? is the programmable decimation ratio, which is equal to 3840/owr when frs = 0 and 3200/owr when frs = 1. the converter?s digital fi lters scale with mclk. for example, with an out put word rate of 120 sps, the filter?s corner freque ncy is at 31 hz. if mclk is increased to 5.0 mhz, the owr increases by 1.0175 percent and the filter ?s corner frequency moves to 31.54 hz. note th at the converter is not specified to run at mclk clock frequencies greater than 5 mhz. figure 13. digital filter response (word rate = 60 sps) -120 -80 -40 0 gain (db) 0 60 120 180 240 300 frequency (hz) frs = 0 -120 -80 -40 0 04080120 frequency (hz) gain (db) flatness frequency db 2-0.01 4-0.05 6-0.11 8-0.19 10 -0.30 12 -0.43 14 -0.59 16 -0.77 19 -1.09 32 -3.13 figure 14. 120 sps filter magnitude plot to 120 hz -180 -90 0 90 180 0 30 60 90 120 frequency (hz) phase (degrees) figure 15. 120 sps filter phase plot to 120 hz note: see the text regarding the sinc 3 filter?s decimation ratio ?d?. sinc 5 1 z 80 ? ? () 5 1 z 16 ? ? () 5 ------------------------- - 1 z 16 ? ? () 3 1 z 4 ? ? () 3 ------------------------- - 1 z 4 ? ? () 2 1 z 2 ? ? () 2 ----------------------- 1 z 2 ? ? () 3 1 z 1 ? ? () 3 ----------------------- = sinc 3 1 z d ? ? () 3 1 z 1 ? ? () 3 ------------------------ - = figure 16. z-transforms of digital filters
cs5530 28 ds742a1 2.9 clock generator the cs5530 includes an on-chip inverting amplifi- er which can be connected with an external crystal to provide the master clock for the chip. figure 17 illustrates the on-chip oscill ator. it includes loading capacitors and a feedback resistor to form a pierce oscillator configuration. the chips are designed to operate using a 4.9152 mhz cr ystal; however, oth- er crystals with freque ncies between 1 mhz to 5 mhz can be used. one lead of the crystal should be connected to osc1 and the other to osc2. lead lengths should be minimize d to reduce stray capac- itance. note that while us ing the on-chip oscillator, neither osc1 or osc2 is capable of directly driv- ing any off chip logic. wh en the on-chip oscillator is used, the voltage on os c2 is typically 1/2 v peak-to-peak. this signal is not compatible with external logic unless additi onal external circuitry is added. the osc2 output s hould be used if the on- chip oscillator output is used to drive other circuit- ry. the designer can use an external cmos compati- ble oscillator to drive osc2 with a 1 mhz to 5 mhz clock for the adc. the external clock into osc2 must overdrive the 60 microampere output of the on-chip amplifier. this will not harm the on- chip circuitry. in this sc heme, osc1 should be left unconnected. 2.10 power suppl y arrangements the cs5530 is designed to operate from single or dual analog supplies and a single digital supply. the following power supply connections are possi- ble: va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v va+ = +3 v; va- = -3 v; vd+ = +3 v a va+ supply of +2.5 v, +3.0 v, or +5.0 v should be maintained at 5% tolerance. a va- supply of -2.5 v or -3.0 v should be maintained at 5% tol- erance. vd+ can extend from +2.7 v to +5.5 v with the additional restriction that [(vd+) - (va-) < 7.5 v]. figure 18 illustrates the cs5530 connected with a single +5.0 v supply to meas ure differential inputs relative to a common mode of 2.5 v. figure 19 il- lustrates the cs5530 connected with 2.5 v bipolar analog supplies and a +3 v to +5 v digital supply to measure ground referenced bipolar signals. fig- ures 20 illustrates the cs 5532 connected with 3 v analog supplies and a +3 v digital supply to mea- sure ground referenced bipolar signals. osc1 mclk note : 20 pf capacitors are on chip and should not be added externally. 1 m ? osc2 20 pf 20 pf + - v th ~ ~ 60 a figure 17. on-chi p oscillator model
cs5530 ds742a1 29 osc2 vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5530 osc1 cs 10 ? +5 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 10 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 19 7 a0 8 a1 c1 c2 4 22 nf 18 nc nc figure 18. cs5530 configured with a single +5 v supply osc2 vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5530 osc1 cs +2.5 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 1 0 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 19 7 a0 8 a1 c1 c2 4 22 nf -2.5 v analog supply 18 +3 v ~ +5 v digital supply nc nc figure 19. cs5530 configured with 2.5 v analog supplies
cs5530 30 ds742a1 osc2 vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5530 osc1 cs 10 ? +3 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 10 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 19 7 a0 8 a1 c1 c2 4 22 nf -3 v analog supply 18 nc nc figure 20. cs5530 configured with 3 v analog supplies
cs5530 ds742a1 31 2.11 getting started this a/d converter has se veral features. from a software programmer?s prospective, what should be done first? to begin, a 4.9152 mhz or 4.096 mhz crystal takes approxima tely 20 ms to start. to accommodate for this, it is recommended that a software delay of approx imately 20 ms be inserted before the start of the processor?s adc initializa- tion code. next, since th e cs5530 does not provide a power-on-reset function, th e user must first ini- tialize the adc to a known state. this is accom- plished by resetting the ad c?s serial port with the serial port initializati on sequence. this sequence resets the serial port to the command mode and is accomplished by transm itting 15 sync1 com- mand bytes (0xff hexade cimal), followed by one sync0 command (0xfe he xadecimal). once the serial port of the adc is in the command mode, the user must reset all the in ternal logic by performing a system reset sequence (see 2.3.2 system reset sequence). after the conve rter is properly reset, the configuration register bits should be configured as appropriate, for exampl e, the voltage reference selection, word rate, signal polarity(unipolar or bi- polar) should be configured. calibrations or conversions can then be performed as appropriate. 2.12 pcb layout for optimal performance, the cs5530 should be placed entirely over an analog ground plane. all grounded pins on the adc, including the dgnd pin, should be connected to the analog ground plane that runs beneath th e chip. in a split-plane system, place the analog-di gital plane split imme- diately adjacent to the digital portion of the chip.
cs5530 32 ds742a1 3. pin descriptions clock generator osc1; osc2 ? master clock an inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the devic e. alternatively, an external (cmos compatible) clock (powered relative to vd+) can be supplied into the osc2 pin to provide the master clock for the device. control pins and serial data i/o cs ? chip select when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. sdi ? serial data input sdi is the input pin of the serial input port. da ta will be input at a rate determined by sclk. sdo ? serial data output sdo is the serial data output. it will output a high impedance state if cs = 1. sclk ? serial clock input a clock signal on this pin determines the input/ output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. a0 ? logic output (analog), a1 ? logic output (analog) the logic states of a1-a0 mimic the a1-a0 bits in the configuration register. logic output 0 = va-, and logic output 1 = va+. 1 2 3 4 5 6 7 813 14 15 16 17 18 19 20 vref+ vref- sclk cs dgnd a1 a0 va- va+ c2 c1 ain1- ain1+ 9 10 11 12 sdo osc1 osc2 serial data input logic output (analog) positive analog power amplifier capacitor connect amplifier capacitor connect differential analog input chip select voltage reference input voltage reference input serial clock input positive digital power digital ground serial data out master clock cs5530 differential analog input nc nc sdi vd+ negative analog power master clock logic output (analog)
cs5530 ds742a1 33 measurement and reference inputs ain1+, ain1- ? differ ential analog input differential input pins into the device. vref+, vref- ? voltage reference input fully differential inputs which establish the voltage reference for the on-chip modulator. c1, c2 ? amplifier capacitor inputs connections for the instrumentation amplifier?s capacitor. power supply connections va+ ? positive analog power positive analog supply voltage. vd+ ? positive digital power positive digital supply voltage (nominally +3.0 v or +5 v). va- ? negative analog power negative analog supply voltage. dgnd ? digital ground digital ground. 4. specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the adc transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full- scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full-scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin.). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs.
cs5530 34 ds742a1 5. package drawings notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowa ble dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of t he lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.272 0.295 6.90 7.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 l 0.025 0.040 0.63 1.03 0 8 0 8 20 pin ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5530 ds742a1 35 6. ordering information 7. environmental, manufa cturing, & handling information model number bits channels linearity error (max) temperature range package cs5530-cs 24 1 0.003% 0 c to +70 c 20-pin 0.2" plastic ssop CS5530-CSZ 24 1 0.003% 0 c to +70 c 20-pin 0.2" plastic ssop, lead free model number peak reflow temp msl rating max floor life cs5530-cs 240 c 2 365 days CS5530-CSZ 260 c 3 7 days
cs5530 36 ds742a1 revision history revision date changes a1 oct 2006 advance release contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject t o change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtai n the latest version of relevant info r mation to verify, before placing orders, that information being relied on is current and complete. all products are sold subjec t to the terms and conditions of sale supplie d at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no r esponsibility is assumed by cirrus for th e use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringeme nt of patents or other rights of third partie s this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyright s trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information con tained herein and gives consent for copie s to be made of the information only for use within your organization with respect to cirrus integrated circuits or other product s of cirrus. this consent does not exten d to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for re sale. certain applications us ing semiconductor products may invo lve potential risks of death, personal injury, or severe prope r ty or environmental damage (?critical ap plications?). cirrus products are not desi gned, authorized or warranted for use i n aircraft systems, military applications, products surgically implanted into the body, automotive safety or security device s life support products or other critical applications. inclusio n of cirrus products in such app lications is understood to b e fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implie d warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer us es or permits the use of cirrus prod ucts in critical app lications, custo m er agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from an y and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are tradem arks of cirrus logic, inc. all other brand and product names in this document may be trademarks o service marks of their respective owners. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corporation.

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